Recent years have seen advancements in the field of electronic circuits and packaging of these electronic circuits. Advancements in the Very Large Scale Integrated Circuits (VLSI) have led to miniaturization of these electronic circuits. Due to this, the electronic circuits which were implemented on Printed Circuit Boards (PCB) are now being implemented on a single semiconductor wafer. Typically, an electronic circuit implemented on a single semiconductor wafer is known as an Integrated Circuit (IC). Further, the process of implementing the electronic circuit having electronic components on a single semiconductor wafer is known as Fabrication. The conventional fabrication process is explained in conjunction with FIG. 1a, FIG. 1b, and FIG. 1c. 
FIG. 1a and FIG. 1b are cross sectional diagrams of a semiconductor wafer representing fabrication steps being performed on the semiconductor wafer, in accordance with the conventional technique for fabricating an IC.
FIG. 1c is a cross sectional diagram of a fabricated semiconductor wafer, in accordance with the conventional technique for fabricating an IC.
FIG. 1a shows a semiconductor wafer 102 that has various electronic components (not shown in the figure) fabricated on its front surface 108 and its back surface 110. These electronic components, on front surface 108 and back surface 110 of semiconductor wafer 102, need to interact with each other and thus, need to be connected. For connecting the electronic components on front surface 108 and back surface 110 of semiconductor wafer 102, a via hole 106 is etched on the surface of semiconductor wafer 102. Thereafter, a seed metal layer 112 as shown in FIG. 1b is deposited on back surface 110 of semiconductor wafer 102. Seed metal layer 112 extends through via hole 106, to a capture pad 104. Thereafter, a metal layer 114 (as shown in FIG. 1c) is deposited on seed metal layer 112 which acts as an adhesive for binding metal layer 114 on back surface 110. While forming metal layer 114 (which is typically Gold (Au)) is deposited on back surface 110 of semiconductor wafer 102. Further, metal layer 114 extends along the wall of via hole 106 for electrically connecting the electronic components on back surface 110 of semiconductor wafer 102 to the electronic components on front surface 108 of semiconductor wafer 102. The process of depositing metal layer 114 for electrically connecting the electronic components on back surface 110 of semiconductor wafer 102 to the electronic components on front surface of semiconductor wafer 102 is known as metallization.
The aforesaid conventional techniques focus on depositing metal layer 114 along the walls of via hole 106 for connecting the electronic components on back surface 110 of semiconductor wafer 102 to the electronic components on front surface 108 of semiconductor wafer 102. This is achieved by depositing metal layer 114 on entire back surface 110 of semiconductor wafer 102. As a result, a large amount of metal used while depositing metal layer 114 gets wasted and it unnecessarily increases the overall fabrication cost.
In view of this, the present invention proposes an improved method of metallization such that the overall fabrication cost is reduced to a great extent. Accordingly, a huge amount of metal can be saved during metallization.